This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to high density structures used in system on chip architectures.
System on chip architectures are used for forming monolithic integrated circuits that incorporate both memory and logic functions on the same semiconducting substrate. System on chip architecture poses several problems to traditional integrated circuit process design, because the processes traditionally used to fabricate memory devices are not well adapted to the formation of logic devices. This is because the memory devices tend to have different design goals than the logic devices. For example, reducing leakage is a primary design goal of a memory device, whereas high switching speed is a design goal of a logic device.
The structures formed in the different semiconducting devices, such as gate oxide thickness, tend to favor either one goal or the other, but typically do not favor both. This same condition exists for many other structures that are seemingly common between memory and logic devices, in that each type of device may utilize a common structure or material, but the desired form of the structure is somewhat different for each type of device. Thus, as mentioned above, a traditional logic process sequence or flow, such as a CMOS process flow, is not well adapted to forming the memory devices in a system on chip architecture.
There also exist additional constraints that are more common to a wide variety of architectures, such as space limitations, otherwise referred to as device density. There is a continual desire to produce faster and otherwise more powerful integrated circuits, while at the same time reducing other factors such as power consumption, heat dissipation, and circuit size. One way in which these goals can be met, at least in part, is to reduce the surface area on the substrate that is required for a given circuit structure. Unfortunately, reducing the surface area of a structure also tends to impact other parameters of the structure, such as electrical characteristics.
Thus, there is a need for structures and process flows by which memory devices can be fabricated concurrently with logic devices while not excessively increasing the number of required process steps, and by which structures can be reduced in size without adversely impacting their electrical parameters.
The above and other needs are met by a memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.
In this manner, a capacitor such as for a high density memory cell that uses a planar MOS capacitor as a storage element (called a C-RAM herein) can be formed in a CMOS process flow, where the capacitor has a larger surface area, and hence a larger capacitance, than would a capacitor formed in just the projected surface area. In other words, by etching down into the silicon substrate within the projected surface area, a greater effective surface area for the capacitor is realized, without using a larger projected surface area. Thus, a high capacitance is realized within a given projected surface area, and the device density of the integrated circuit is thereby increased.
Further, the dielectric layer grows faster on the etched surface of the substrate in the capacitor region than it does on the top surface of the substrate in the gate area, thereby forming a thicker dielectric layer in the capacitor than on other portions of the substrate, such as in gate areas. Thus, the gate dielectric can be concurrently formed with the capacitor dielectric, while each retains different electrical properties that are preferred for the different structures so formed.
In various preferred embodiments of the invention, the lower electrically conductive plate is formed with one of N doping or P doping. The dielectric layer is preferably formed of silicon oxide. Most preferably, the top electrically conductive plate comprises doped polysilicon, but in alternate embodiments is formed of metal. The lower electrically conductive plate is preferably etched along the (111) planes of the silicon substrate, and the top surface of the silicon substrate is along the (100) plane.
According to another aspect of the invention there is described a method of forming a capacitor. A mask is formed on the (100) surface of a silicon substrate to expose a capacitor area, and the capacitor area of the surface of the silicon substrate is cleaned. The capacitor area is cleaned with an etchant that preferentially etches the silicon substrate with a high degree of selectivity along the (111) planes of the silicon substrate. Such etching forms lower capacitor surfaces that are disposed at about fifty-five degrees from the surface of the silicon substrate. The etch is self limiting and substantially stops when the capacitor surfaces are bounded by edges of the capacitor area and one another. The silicon substrate in a portion disposed under the lower capacitor surfaces is altered so as to be electrically conductive. The mask is removed from the surface of the silicon substrate. A dielectric layer is formed on the lower capacitor surfaces, and a top capacitor plate is formed of an electrically conductive material on the dielectric layer.